Photo Credit: WD The sixth generation of BiCS memory will feature 162 active layers and will be used for 1Tb 3D NAND QLC with a 68mm² die size. It should also offer higher I / O performance, which will make better use of the PCI Express 5.0 interface. Although 176-layer chips from other manufacturers have already been announced, WD's proposal differs in the small size of the memory cells, which should make the devices easier and cheaper to manufacture. Mass production of memories in QLC and TLC configurations will begin at the end of 2022 (corresponding to the second quarter of fiscal year 2023).
Photo Credit: WD Still further, WD will make 3D NAND memories with over 500 layers using advanced techniques, but to see them in action we will have to wait until at least 2030, as stated by Siva Sivaram, president of Western Digital's "technology and strategy" division:
You can see [that] in the next 10+ years we have a good roadmap for developing and using new technologies to get there up to more than 500 layers. We started with two-level 3D NAND to scale the cell pitch and will probably introduce wafer bonding, multi tearing, multi wafer bonding. These technologies are already being worked on in order to introduce them in the right node […].