Credit: AnandTech / Gregory Bryant (Intel ) According to the poster, Intel is targeting "80G PHY technology", which means an 80Gb / s connection, double the bandwidth of today's Thunderbolt 4 and USB 4 connections. The poster also says "USB 80G is intended to support the existing USB-C ecosystem ", which means Thunderbolt 5, like its predecessors, will use a USB-C connector.
Launched in 2011, Thunderbolt is Intel's high-speed connection standard currently in its fourth incarnation, although it offers the same 40Gb / s bandwidth and feature set as Thunderbolt 3. By doubling the bandwidth to 80Gb / s, Thunderbolt 5 could potentially offer ag frequencies. higher clock rates for 4K and 8K monitors, which now support up to 120 and 60Hz respectively.
To get more bandwidth on Thunderbolt 5, it appears the protocol will use PAM-3 modulation. So far, in protocols like USB, PCIe, etc., we have seen non-return-to-zero (NRZ) and PAM-4 (Pulse Amplitude Modulation) implementations. NRZ signals are binary, i.e. only 0 and 1, while PAM-4 signals are represented in two-bit formats (such as 01, 11, 11, 00). If you are more interested in the more technical aspects, we advise you to consult this blog.
Credit: Samtec The new PAM-3 uses the states -1, 0 and +1. This approach lies just halfway between NRZ and PAM-4, but the implementation of this signaling technique is much simpler than PAM-4 while maintaining high bandwidth.
The leaked slide it also revealed that “[…] the N6 test chip focusing on the new PHY technology is working in […] showing promising results”. While we can't see the full picture, it means Thunderbolt 5 PHY (physical layer) is already performing as expected and producing the desired results. Since we know that N6 is TSMC's 6nm manufacturing node, we can assume that Intel leveraged TSMC's foundries to produce chips for the Thunderbolt 5 test.
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