AMD's new Ryzen chiplets with 3D V-Cache promise major improvements

AMD's new Ryzen chiplets with 3D V-Cache promise major improvements

At Computex 2021, AMD announced that 3D-stacked chiplets based on the Zen 3 architecture will go into production this year. The latter will allow you to add an additional 64MB of 7nm SRAM cache (called 3D V-Cache) stacked vertically on top of the Core Complex Die (CCD) to triple the amount of L3 cache for the CPU cores. This technique can provide up to 192MB of L3 cache for Ryzen processors, a substantial improvement over the current 64MB limit.

AMD CEO Lisa Su also showed off the Ryzen 9 5900X prototype chip working in a demonstration that highlighted the best performance obtainable in the gaming field, equal, in this case, to an average of 15% at 1080p resolution. This is the kind of gain we typically associate with a new CPU and / or process node microarchitecture, but AMD has accomplished this feat with the same 7nm node and Zen 3 architecture already used on current Ryzen 5000 series models. br>
AMD ties the 3D cache to the top of the Ryzen CCD with TSV (Through Silicon Vias) which allows for up to 2TB / s of bandwidth between the chip and the cache. This technique is made possible by TSMC's 3DFabric technology:

AMD 3D Chiplet Technology: A packaging breakthrough for high-performance computing.

- AMD (@AMD) June 1, 2021

AMD has also thinned the 3D cache die and added structural silicon to the chip, resulting in a processor that looks visually identical to the standard one. In the Ryzen 9 5900X prototype shown by Su you can see the 6 × 6mm hybrid SRAM attached to the top of the chiplet. The end devices will have 96MB of cache per CCD, for a total of nearly 192MB on a 12- or 16-core Ryzen 5000 CPU.

AMD used a hybrid bonding approach with TSV that provides over 200x the interconnect density of 2D chiplets, with a 15x improvement in interconnect density over 3D micro-bump implementations and an improvement in three times in interconnect energy efficiency.

Su said these advances were made possible by the use of a microbump-free die-to-die interface that uses a direct copper-to-copper bond to improve temperature, density and interconnection pitch, as well as producing incredible energy advances. Su said this combination of features made this approach the most advanced and flexible active-on-active silicon stacking technology in the world.

Su compared the Ryzen 9 5900X prototype to the new 3D V-Cache against a standard 5900X, with both chips locked at 4.0GHz clock speeds, recording 12% better performance on Gears 5, but also testing other titles, such as Dota 2, Monster Hunter World, League of Legends and Fortnite, the average gain was 15%.

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